Typically, multi-core processors, such as the Intel® Core™ i7 Processor, have a multi-tier memory hierarchy. Each core in the multi-core processor may have a dedicated hierarchy of cache (Level 1 (L1)-Level 2 (L2)) and may also share a lower level cache (Level 3 (L3)). The lower level cache tends to have an increased chip area, and therefore, the lower level cache tends to increase the costs associated with multi-core processors.
in some prior art systems, the embedded cache (e.g., L1-L3) tend to utilize static random access memory (SRAM), SRAM may be desirable because it is logic compatible and fast. Still, SRAM has a large size area that results in a high cost, and furthermore, SRAM tends to leak power. Therefore, the use of SRAM for the lower level cache of a multi-core processor may be undesirable due to, at least, an increased cost and power consumption.
Other prior art systems may have a hybrid cache (e.g., through silicon stacking (TSS) or package on package (PoP)). Hybrid cache refers to a system that utilizes different types of memory in the cache levels. The hybrid cache may be configured as an inter-level hybrid cache, intra-level hybrid cache, or three-dimensional (3D) hybrid cache.
FIG. 1 illustrates an example of a prior art inter-level hybrid cache 100. As illustrated in FIG. 1, the core 102 (which includes L1) and L2 cache 104 may use SRAM, and the L3 cache 106 may use a different type of memory, such as embedded dynamic random access memory (eDRAM), MRAM, or phase-change random access memory (PRAM). The inter-level hybrid cache 100 is not limited to the memory types discussed in FIG. 1 and may utilize various memory types for each cache layer 102-106.
FIG. 2 illustrates an example of a prior art intra-level hybrid cache 200. As illustrated in FIG. 2, the core 202 (with L1) and a first L2 cache 204 may use SRAM. Specifically, the first L2 cache 204 may be configured for high speed memory, and therefore, the first L2 cache 204 may utilize SRAM. Moreover, a second L2 cache 206 may be configured for slow memory, and therefore, the second L2 cache 206 may be a type of memory that is different from the type of memory used in the first L2 cache 204. For example the second L2 cache 206 may use eDRAM, MRAM, or PRAM. The intra-level hybrid cache 200 is not limited to the memory types illustrated in FIG. 2 and may utilize various memory types for each cache layer 202-206.
The inter-level or intra-level hybrid cache may use various memory technologies. Still, the inter-level cache and intra-level hybrid cache are complex and have increased fabrication costs due to the monolithic integration of various memory technologies. Therefore, the use of an inter-level or intra-level hybrid cache for the lower level cache of a multi-core processor is undesirable due to the increased costs and complexity.
FIG. 3 illustrates an example of a prior art 3D hybrid cache 300. As illustrated in FIG. 3, the core 302 (with L1) and a first L2 cache 304 may use SRAM. Moreover, a second L2 cache 306 may be configured to utilize slow memory, and therefore, the second L2 cache 306 may utilize a different type of memory, such as eDRAM, MRAM, or PRAM. Furthermore, the core 302, first L2 cache 304, and second L2 cache 306 may be defined on a single chip. The L3 cache 308, may use a memory such as PRAM, and may be defined on a separate die that is connected to the chip including the core 302, first L2 cache 304, and second L2 cache 306. That is, the L3 cache 308 is on a layer (e.g., chip) that is different from the layer including the core 302, first L2 cache 304, and second L2 cache 306.
The 3D hybrid cache may be desirable due to the use of heterogeneous memories in multiple layers and high-density memories in known good die. Still, a 3D hybrid cache specifies a multi-die solution that is stacked. Accordingly, the 3D hybrid cache may increase costs due to the stacked die. Furthermore, the stacking of the die also increases the overhead (e.g., cost, reliability).